pastermil@sh.itjust.works to Programmer Humor@lemmy.ml · 1 year agoSome Mnemonicssh.itjust.worksimagemessage-square19linkfedilinkarrow-up1348arrow-down16
arrow-up1342arrow-down1imageSome Mnemonicssh.itjust.workspastermil@sh.itjust.works to Programmer Humor@lemmy.ml · 1 year agomessage-square19linkfedilink
minus-square9point6@lemmy.worldlinkfedilinkarrow-up26·1 year agoI still don’t know why this architecture went for a Double XOR as the NOP, I guess they were just flexing that the reference chip design could do both in a single cycle
I still don’t know why this architecture went for a Double XOR as the NOP, I guess they were just flexing that the reference chip design could do both in a single cycle